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Phase-Locked Loop Circuit Design Dan H. Wolaver
Publisher: Prentice Hall

This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. Figure 1 contains a block diagram of a basic PLL frequency multiplier. PLL is a closed loop system designed to lock the output frequency and phase of to the frequency and phase off an input signal. The part about the circuit design is the part which scares me, because I don't have any experience with circuit design. I've read a lot of theory and math about Phase Locked Loops. Each of these applications demands different characteristics but they all use the same basic circuit concept. The Silicon Creations Fractional-N PLL (block diagram shown in Figure 2) suppresses this noise with the addition a feed-forward compensator that feeds directly into the loop filter, and is able to achieve jitter in Fractional mode very close to that achieved in integer mode. Other carrier-grade features include SONET-compatible jitter peaking (0.1dB max) and circuitry to minimise output clock phase transients during reference switching. Long term jitter as small as 2ps RMS has been Thus the PLL Period Jitter (PJ, also known as short term jitter) must be known in order for the circuit to have sufficient timing margin. (Bias-tee circuit) about 1~3 mVrms or less bypass capacitor. A complete overview of both system-level and circuit-level design and analysis are covered. BH1417 – Stereo PLL Transmitter IC (Case SOP22) 1x 7.6MHz Crystal 1x MPSA13 – NPN Darlington Transistor 1x 2.5 Turns Variable Coil 1x MV2109 – Varicap Diode 1x 4-DIP Switch ANT – 30 cm of copper wire. (50 Hz ~ 1 MHz) to Baseband input. The Phase Locked Loop is an important building block of linear systems. The second step is to design the optimal loop filter for lower phase/spurious noise and faster frequency transient response. Evaluating VCO performance is the first step toward designing a better.